Interrupt nesting
Letting a higher-priority interrupt preempt an interrupt handler that is already running.
Without nesting, an urgent interrupt waits until the current handler finishes, so the worst-case response time is as long as the longest handler. With nesting, the CPU saves the handler's state too and jumps onward. On Cortex-M the NVIC does this in hardware based on priority levels. On AVR interrupts are disabled on entry, and anyone who wants nesting has to re-enable them with sei() themselves — at their own risk.
The price is stack. Each level pushes a new frame on top of the last, and the worst-case depth is every level stacked at once. That case rarely happens on the bench and readily happens in the field, which is why stack painting and careful priority planning go hand in hand with nesting.