NVIC

It tracks which interrupts are enabled, which are pending and what priority each one has, and it lets a more important interrupt pre-empt a less important one halfway through its handler — hence "nested". On entry the hardware pushes eight registers onto the stack by itself, which is why Cortex-M interrupt handlers can be ordinary C functions with no assembly wrapper. On a Cortex-M3 or M4 it takes twelve cycles from signal to first instruction.

Two tricks shave latency further: tail-chaining jumps straight into the next pending handler without unstacking and restacking, and late arrival lets a higher-priority interrupt take over while the stack is still being written. The classic trap is that a lower number means a higher priority, and that vendors only implement the top bits — four out of eight on STM32.