Interrupt latency
The time from an event raising an interrupt to the first instruction of its handler executing.
The hardware part is fixed and documented: a Cortex-M3 or M4 needs twelve clock cycles, a Cortex-M0 sixteen, and by then the core has already stacked the registers. On a PC, with caches, deep pipelines and an operating system in the way, the same thing is measured in microseconds and varies wildly.
What really decides it is the software. Every critical section with interrupts disabled, every higher-priority handler already running and every flash read with wait states adds on top. That's why serious RTOS vendors quote worst case rather than typical, and the spread between best and worst — the jitter — often matters more than the average. A motor controller that responds in 2 µs some of the time and 40 µs at other times is harder to regulate than one that always takes 10.