Chiplet interconnect
The high-speed link that connects multiple chiplets (separate silicon dies) in a package into a working processor. Crucial for chiplet design performance — the link must not become a bottleneck compared to a monolithic chip.
Challenge: two dies on the same substrate must communicate with nearly as low latency/high bandwidth as if they were one chip, or the benefit is lost. Solutions: AMD Infinity Fabric (organic substrate routing), Intel EMIB (a silicon bridge embedded in the substrate), TSMC's interposer-based (CoWoS). UCIe (2022) is an open industry standard for die-to-die links → meant to create a market where chiplets from different vendors can be mixed. Energy per bit + bandwidth per mm are the key metrics. It enables mixing process nodes (expensive cores in 3nm, cheap I/O in 6nm) in the same chip.