Advanced packaging
Techniques to integrate multiple chiplets on the same substrate or stack them 3D. CoWoS (TSMC), Foveros (Intel), EMIB (Intel), SoIC (3D stacking). Bottleneck for AI-chip production 2024-2025.
CoWoS (Chip-on-Wafer-on-Substrate): silicon interposer between chip + substrate, high-density interconnects. Used for H100, MI300X. Foveros: 3D stacking — Intel Meteor Lake. EMIB: silicon bridge between chiplets without full interposer (cheaper). TSMC CoWoS capacity sold out 2024 → Nvidia AI-chip supply constrained (not by silicon, by packaging). Capex explosion: TSMC investing $30B+ in new CoWoS facilities. Modern: Chip-on-Substrate (CoS), sintered-die-stacking, hybrid bonding. Future: backside power delivery (Intel 18A) is the next packaging revolution.