CoWoS
Chip-on-Wafer-on-Substrate — TSMC's 2.5D advanced-packaging tech. Multiple chiplets (GPU die + HBM stacks) sit on a silicon interposer that provides ultra-high-density interconnects. Bottleneck for AI-chip supply 2024-2025.
Powers Nvidia H100/B100/B200, AMD MI300X. Interposer size: 80x80mm for the latest, requires advanced lithography. Capacity issue: TSMC CoWoS-fab could produce ~10-15k wafers/month 2023 → all subscribed by Nvidia. Expansion to 25k+ 2024-2025. Cost: ~$5000+ per packaged chip in extra packaging cost beyond die cost. Competitors: Intel Foveros (3D), Samsung X-Cube. Modern AI supply-chain insight: silicon-fab is not the bottleneck, packaging is. TSMC builds 2 new CoWoS-fabs ($30B investment) — bottleneck easing 2026+.