STA Static timing analysis
Verifying that a chip meets its timing by computing every path in the design mathematically, rather than simulating it with test data.
The tool sums cell and wire delays up to each endpoint, compares that against the time available and reports the margin — negative margin meaning a violation. Its strength is exhaustiveness: a simulation only checks the paths its test data happens to exercise, while the analysis covers all of them, and there are billions. The run is done across every combination of process, voltage and temperature and checks both setup and hold. The limitation lies not in the mathematics but in the inputs. The analysis needs a description of clocks, of paths that are never active, and of paths permitted to take several cycles, and by far the commonest reason it gives a wrong answer is an incorrect or missing such declaration — either hiding a real violation or generating a thousand imaginary ones.