Setup and hold time
The two timing requirements on a flip-flop's input: data must be stable for a period before the clock edge and for a period after. Violate either and you risk metastability.
The crucial thing is that the two failures behave entirely differently. A setup violation means the signal didn't arrive in time, which is a question of how long the clock period is — lower the clock frequency and the problem disappears, which is exactly what happens when a processor can't hold its top speed. A hold violation means the opposite, that data changed too soon after the edge, and it is independent of clock period: a slower clock doesn't help at all. The fix is inserting delay into the data path. The consequence is that a hold violation escaping into silicon cannot be worked around — the chip is simply broken. Static timing analysis checks both across all process, voltage and temperature corners.