Metastability
A flip-flop whose input changed too close to the clock edge can settle into a state that is neither a one nor a zero, and stay there for an indeterminate time before resolving arbitrarily.
It cannot be designed away. The phenomenon follows from the circuit having an unstable equilibrium point between its two stable states, rather like a pencil balanced on end, and for any conceivable circuit there is an input timing that puts it there. Instead it is handled statistically: the probability that it is still undetermined decays exponentially with the time it is given, and from the flop's characterised time constant together with the clock and data rates an expected mean time between failures is computed. Adding a second flip-flop gives the first one an entire clock period to resolve, which typically moves that interval from seconds to millions of years.