Clock domain crossing CDC
A signal passing between two parts of a chip clocked by independent clocks. One of the few classes of bug that never shows up in ordinary simulation.
Because the clock edges bear no fixed relationship to each other, the receiving flip-flop will sooner or later be sampled just as its input changes, violating its setup and hold times and going metastable. For a single bit a synchroniser of two flip-flops in series suffices. For several bits at once it doesn't help at all — different bits can land on different sides of the edge, so the receiver sees a value that never existed — and you must either handshake or use an asynchronous FIFO with Gray-coded pointers, where only one bit changes at a time. Finding these faults requires dedicated static analysis plus randomised delay injection.