RISC vs CISC
The classic design-philosophy clash: RISC (Reduced Instruction Set Computer) with few, simple, uniform instructions, versus CISC (Complex Instruction Set Computer) with many, powerful, varying ones. ARM/RISC-V are RISC; x86 is CISC. In practice the line has blurred.
Original idea: CISC (x86) — complex variable-length instructions that do a lot per instruction (good when memory was expensive and compilers were simple). RISC (ARM, RISC-V) — few, fixed, simple instructions that each do little but can be pipelined and decoded simply and in parallel. The RISC argument won a lot: simple, regular decoding is easier to make wide and frugal (one reason for ARM's energy efficiency and Apple Silicon's wide cores). Modern reality: the line is blurred — modern x86 CPUs internally decode their complex instructions into simple, RISC-like micro-operations (µops) and run them on a RISC-like core. So "x86 is internally RISC" is partly true. The debate mostly lives on in the decoding cost (x86's variable length is still expensive to decode widely). A central, often misunderstood, architecture question. Related to ISA and decode stage.