Decode stage
The step where fetched instructions are interpreted and translated into the internal micro-operations (µops) the CPU's execution units actually understand. For x86 this is unusually complex because the instructions are variable-length and of varying complexity.
Mechanic: the decoder takes the raw instruction bytes and determines what they mean — which operation, which operands — and breaks them down into one or more simple, fixed micro-operations. The x86 challenge: instructions are 1-15 bytes long (you don't know where the next one starts until you've decoded the current one), and a single complex instruction can become many µops → decoding is expensive and hard to parallelize. RISC architectures (ARM, RISC-V) have fixed, simple instructions that are much easier to decode many in parallel. Solutions in x86: multiple decoders, a micro-op cache (skip decoding for hot code), and a microcode ROM for the most complex instructions. The decode width is often a front-end bottleneck. A central distinction in the RISC-vs-CISC debate. Related to instruction fetch and RISC vs CISC.