Instruction fetch
The first step in the CPU's pipeline, where instructions are fetched from memory (the instruction cache) to be fed into the rest of the machinery. How quickly and correctly the front-end can fetch instructions sets the ceiling for how much work the core can do.
Mechanic: a "program counter" points to the next instruction; the fetch unit reads a block of instructions from the L1 instruction cache (I-cache) each cycle. Since modern cores want to fetch many instructions per cycle and can't wait for jumps, fetching is tightly interwoven with branch prediction (BTB/RSB) that steers where the next fetch happens — the front-end "runs ahead" and fetches speculatively along the predicted path. Bottlenecks: an I-cache miss stalls the whole core (no instructions to run), and incorrect branch prediction means you've fetched the wrong code (it must be discarded). The micro-op cache can bypass fetch/decode for hot code. The front-end width (instructions fetched/cycle) is a fundamental dimension of a microarchitecture. Related to decode stage and micro-op cache.