Die shrink
Manufacturing an existing chip design on a smaller/newer process node, so the transistors get smaller. The result: lower power consumption, less silicon area (cheaper per chip), and often higher clock speeds — without changing the architecture itself.
Mechanic: the same logical design is "shrunk" to a finer node (e.g. 7 nm → 5 nm). Historically the engine behind Moore's law: each node gave more, faster, lower-power transistors. Win: more performance per watt, more chips per wafer (lower cost), cooler operation. Classic pattern: Intel's old "tick-tock" (tick = die shrink of an existing architecture, tock = new architecture). Nowadays pure shrinks get harder and more expensive (physical limits, leakage currents) → the gains per node shrink and the cost soars, which drives chiplets and advanced packaging. Related to process node and EUV.