Spurious interrupt
An interrupt that reaches the CPU even though no source has anything left to say.
The classic case comes from the 8259 controller: if a request line drops between being raised and being acknowledged, the chip has nothing sensible to report and answers with IRQ 7 (or 15) as a fallback. A handler that doesn't check the in-service register then services an interrupt that never happened.
On microcontrollers the usual cause is self-inflicted. The handler clears the peripheral's flag as its very last instruction, but the write is still sitting in a bus buffer when the handler returns. The level-triggered line is still high, so the interrupt fires once more for nothing. The fix is to clear the flag early or add a memory barrier. A floating input without a pull resistor produces the same symptom, with the hardware's enthusiastic help.