Pipeline stall (bubble)
When the CPU pipeline is forced to pause because an instruction can't continue — it's waiting for data, a resource, or the outcome of a jump. The empty gap that results is called a "bubble" and represents wasted clock cycles.
Causes (hazards): data hazard (an instruction needs a result a previous one hasn't produced yet), structural hazard (two instructions want the same hardware resource at once), control hazard (you don't know which instruction comes next until a jump is resolved), and — the most expensive — a cache miss (waiting hundreds of cycles for memory). A stall propagates: the instructions behind it must also wait, and the pipeline fills with bubbles. Countermeasures: forwarding/bypass (send results directly between stages), out-of-order execution (find other work to do during the wait), branch prediction (guess instead of waiting), and prefetching. Minimizing stalls is the whole point of much of modern CPU design. Related to data hazard and forwarding/bypass.