Data hazard
When an instruction in the pipeline needs a data result that a preceding instruction hasn't produced yet. The most common obstacle to running instructions tightly back-to-back — if not handled, the pipeline must stall and wait.
Types: RAW (Read After Write) — the classic and true one: instruction B reads a register that A is about to write, but A isn't done → B must wait for A's result. WAR (Write After Read) and WAW (Write After Write) are "false" dependencies that only arise from reusing the same register, and can be eliminated with register renaming (give them different physical registers). Handling RAW: forwarding/bypass sends the result directly from where it's computed to where it's needed, without waiting for it to be written to the register file — which often eliminates the wait entirely. Out-of-order execution helps by running independent instructions in the meantime. Understanding data hazards is the foundation for understanding why CPUs need forwarding and renaming. Related to forwarding/bypass and control hazard.