L1/L2/L3 cache
The three common cache levels in a modern CPU, from fastest/smallest (L1) to largest/slowest (L3). L1 and L2 are private per core; L3 is usually shared between all cores. Together they form the cache hierarchy that keeps the CPU fed with data.
The levels in detail: L1 — smallest (typically 32-64 kB per core) and fastest (~4 cycles), almost always split into an instruction cache (L1i) and a data cache (L1d) so both can be accessed at once. L2 — medium-sized (256 kB-several MB per core), fast (~10-15 cycles), private per core. L3 ("last level cache", LLC) — large (tens of MB), slower (~40 cycles), shared between all cores (which enables fast data sharing and cache coherence between them). Design nuances: how the levels relate to each other (inclusive vs exclusive), associativity, and AMD's large "3D V-Cache" (extra L3 stacked on top). More/faster cache is often the key to gaming and server performance. The concrete realization of the cache hierarchy. Related to cache hierarchy and inclusive cache.