Inclusive cache
A cache policy where a lower level (e.g. L3) is guaranteed to contain everything in the higher levels (L1/L2) above it. It simplifies cache coherence but "wastes" space through duplication. The opposite is an exclusive cache, which never duplicates.
Inclusive: everything in L1/L2 is also in L3. Advantage: coherence becomes simple — if another core wants to know whether a data line is in this core's private cache it's enough to check the shared L3 (if it's not there, it's nowhere in the core) → you avoid "snooping" each core's private caches. Disadvantage: the same data exists at several levels at once → the effective total cache capacity is reduced (L3 is "wasted" on copies of what's already in L2). An exclusive cache does the opposite: a line exists at exactly ONE level → maximum total capacity, but coherence becomes trickier. There's also a middle ground ("non-inclusive/NINE"). The choice is a classic architecture trade-off: coherence simplicity and latency vs total capacity. Intel long leaned toward inclusive L3, AMD toward exclusive/victim. Related to L1/L2/L3 cache and victim cache.