Issue width
How many instructions (or micro-operations) a CPU core can issue to its execution units per clock cycle. An "8-wide" core can start up to eight operations at once — one of the most fundamental measures of a microarchitecture's capability.
Role: the issue width sets the ceiling for the parallelism in a superscalar core. Wider = potentially more work per cycle = higher IPC (instructions per cycle), which gives performance without raising the clock frequency. But the width must be matched all the way: the front-end must fetch/decode enough instructions, there must be enough execution units, a large enough ROB, and enough registers to rename — otherwise the width goes unused. Apple's M-series cores are notorious for unusually large width (8+), which is a key to their high IPC. Limit: programs' instruction-level parallelism (ILP) is finite → beyond a certain width it gives diminishing returns. Tightly tied to superscalar design and out-of-order. A core parameter in CPU design. Related to superscalar and reorder buffer.