Superscalar
A CPU design that can issue and execute several instructions at once within the same clock cycle, by having multiple parallel execution units. That's why modern cores can do more than one instruction per cycle (IPC > 1).
Mechanic: instead of a single "lane", a superscalar core has multiple ports/units (several ALUs, load/store units, FPUs) and can issue several instructions per cycle if they're independent. Combined with out-of-order and speculation to find enough independent work to feed the units. Metrics: "width" (e.g. 6-wide = up to 6 instructions/cycle) and IPC (instructions per cycle). Win: more work per clock cycle without raising the frequency. Limit: instruction-level parallelism (ILP) in the code is finite → which is why the industry turned to more cores. Apple's and AMD's wide cores are extreme examples. Related to out-of-order and SIMD.