Infinity Fabric
AMD's internal interconnect fabric that ties together CPU core complexes (CCD), the memory controller, and I/O in the Zen architecture. It enables the chiplet design — but its clock (FCLK) becomes a bottleneck for memory latency.
Role: it carries data + cache coherence between chiplets and to memory. On Ryzen, the Infinity Fabric (FCLK) ideally runs at a 1:1 ratio with the memory clock (MEMCLK) — break that ratio (above ~DDR5-6000/6400) and latency drops, which is why "DDR5-6000 CL30" is AM5's sweet spot rather than higher frequency. It scales up to Infinity Fabric between sockets in EPYC servers. The foundation of AMD's cost-effective chiplet strategy (small cheap dies linked together instead of one big expensive one). Intel's equivalent: the Ring Bus (mainstream) / Mesh (server).