CoreSight

Before CoreSight, every silicon vendor rolled its own debug logic and every debugger had to learn every flavour. In 2004 ARM standardised the pieces instead: a Debug Access Port (DAP) that speaks JTAG or SWD to the outside world and exposes one or more access ports onto the system's memory bus, plus a ROM table listing which components exist and where they live.

Everything else hangs off that: ETM for instruction trace, ITM and SWO for printf-style output, DWT for watchpoints and counters, CTI for halting several cores at once. A Cortex-M0 has a handful of these blocks, a phone SoC has hundreds. That's why a single OpenOCD can talk to chips from entirely different vendors — it reads the ROM table and works out the rest on its own.