SystemVerilog
The extension that turned Verilog into both a design and a verification language. In practice two different languages that happen to share a file extension.
The design half is modest in scope but valuable: stricter types, packed structures and enumerations, and blocks like always_ff and always_comb where you declare your intent so the tool can object when the code doesn't match it. Interfaces let related signals be bundled instead of enumerated in every module header. The verification half is considerably larger and object-oriented — classes, inheritance, constrained random stimulus generation, functional coverage measurement and property-based assertions — and it is what the whole of UVM rests on. The split is so pronounced that designers and verification engineers effectively work in separate subsets and often struggle to read each other's code.