RISC-V
More info
- Creator
- UC Berkeley (Krste Asanović et al.)
- Released
- Type
- Instruction Set Architecture (ISA)
- License
- BSD / open
- Website
- riscv.org
- Wikipedia
- en.wikipedia.org
Open ISA — anyone can design CPUs around it, without paying licensing fees to ARM or Intel.
Started as a research project at Berkeley in 2010, became RISC-V International in 2015. Modular: RV32I/RV64I base + optional extensions (M = multiply, F = float, V = vector). SiFive, Espressif (ESP32-C series), Western Digital, Alibaba T-Head — all build RISC-V chips. Big in China due to geopolitical restrictions on ARM. Not the fastest yet, but the momentum is enormous.