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Prefetcher

Hardware På svenska → Updated: 2026-05-29

A mechanism that predicts what data the CPU will soon need and fetches it into the cache in advance — before it's actually requested. Goal: hide the memory latency so the data is already in place when the instruction arrives, and a cache miss is avoided.

Mechanic: hardware prefetchers monitor memory access patterns and extrapolate. The simplest catch sequential access (if you read line N, fetch N+1); more advanced ones detect stride patterns (access with a fixed step, e.g. every 64 bytes — common in loops over arrays) or even irregular patterns. When the pattern is recognized, future lines are fetched in the background while the CPU works, so the latency is hidden. There's also software prefetch (the compiler/programmer inserts explicit prefetch instructions). Trade-off: aggressive prefetching can waste memory bandwidth and pollute the cache with data that's never used (if the guess was wrong). A good prefetcher is often crucial for memory-intensive workloads. Tightly tied to cache miss. Related to cache miss and cache hierarchy.

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