Power gating
An energy-saving technique that turns off the power ENTIRELY to parts of a circuit not being used — not just the clock. It also eliminates leakage current (static power), but the block loses its state and takes longer to wake. More aggressive than clock gating.
Mechanic: a transistor "power switch" disconnects the supply voltage from a block (an idle CPU core, an unused accelerator). Then both dynamic power AND leakage current (the current that leaks even when nothing switches — an ever-growing fraction in modern process nodes) disappear. Trade-off vs clock gating: power gating saves much more (including the leakage), but the block loses all its state (it must be saved/restored) and has a wake-up latency → it only pays off for blocks that are idle long enough. Use case: turning off whole CPU cores when load is low (core parking), or parts of a chip in deep power-saving modes. Together with clock gating and DVFS it forms the basis of modern power management. Related to clock gating and core parking.