Phase-locked loop (PLL)
A feedback circuit that locks its own oscillator to the frequency and phase of an incoming signal, which lets it recover a clock from a data stream.
Three parts are enough: a phase detector comparing the input with the local oscillator, a loop filter that smooths the error, and a voltage-controlled oscillator that speeds up or slows down in response. Frenchman Henri de Bellescize described the principle in 1932 for radio reception. Today PLLs sit in every processor, radio and disk controller.
In digital audio, the PLL is what extracts the sample clock from an S/PDIF or AES3 stream, where the clock is embedded in the data. Loop bandwidth decides the outcome: a wide loop faithfully tracks the sender's jitter, a narrow one filters it out but takes longer to lock. That's why high-end converters run two loops in series, or give up and use an ASRC.