Huge page (TLB)
The use of large memory pages (2 MB or 1 GB instead of the standard 4 kB) to reduce pressure on the TLB. Since each TLB entry then covers much more memory, fewer entries are needed — which gives fewer TLB misses and fewer expensive page table walks.
Mechanic from a hardware perspective: the TLB caches virtual-to-physical translations, but it only has a limited number of entries. With 4 kB pages, one entry covers only 4 kB → a program that touches a lot of memory needs more translations than the TLB holds, causing TLB misses and page table walks (several memory accesses per miss). A single 2 MB huge-page entry covers as much as 512 regular pages → the "TLB reach" is multiplied, the misses plummet. Win: large for memory-intensive workloads (databases, scientific computing, virtual machines) that would otherwise spend noticeable time in page table walks. Trade-off (from the OS side): more internal waste and fragmentation, and THP (transparent huge pages) can cause latency spikes. Here the focus is on the hardware win: better TLB reach. Related to page table walk and TLB.