Exclusive monitor (LDREX/STREX)
ARM's hardware mechanism for atomic read-modify-write: a load tags an address, and the store succeeds only if nobody else touched it in between.
LDREX reads a value and tells the monitor to watch that address. The program computes a new value, and STREX tries to write it back. If anything happened meanwhile — another core wrote there, or an interrupt got in — the store fails, STREX returns 1, and the code loops round to try again. The principle is called load-linked/store-conditional and was already in MIPS; ARM picked it up with ARMv6.
On Cortex-M3 and up, every exception entry clears the monitor, so an increment in the main loop can't collide with the same increment in an ISR. The Cortex-M0 lacks the instructions entirely, which is why atomic operations there are done by masking interrupts inside a critical section.