Dual-bank flash
On-chip flash split into two independent halves, so code can run from one while the other is erased and written.
Ordinary flash has an annoying trait: while a sector is being erased, nothing can be read from the same bank, so the processor stalls until the erase finishes — sometimes for hundreds of milliseconds. With two banks and separate controllers, code keeps executing from one while the other is programmed. It is read-while-write at the chip level.
The big use case is firmware updates. The new image is written to the inactive bank at leisure, verified, and activated by flipping an option byte that decides which bank is mapped at the boot address. Several STM32 families have exactly such a bank-swap bit. If power fails mid-write, the old version is still sitting there untouched. Single-bank chips have to solve the same problem in software, as MCUboot does with a scratch area and considerably more erase cycles.