CPLD
Complex Programmable Logic Device — a small programmable logic chip that keeps its configuration without power and is live the same microsecond the supply comes up.
The CPLD is a scaled-up descendant of the PAL and GAL parts of the 1970s and 80s: a set of macrocells built on sum-of-products logic, tied together by a central interconnect matrix. Unlike an FPGA, the configuration sits in on-chip flash or EEPROM, and pin-to-pin delay is predictable. Classic families are Altera's MAX 7000 and Xilinx's XC9500 and CoolRunner.
The job is glue logic: address decoding, power sequencing on server boards, translating between buses that don't quite fit. Most are programmed over JTAG. The line to FPGAs blurred in 2004 when Altera launched MAX II, which was LUT-based inside yet still sold as a CPLD.