CAS latency (CL)
Column Access Strobe latency — the number of clock cycles between the memory controller requesting a data column and the RAM delivering it. Stated as "CL" in RAM specs (e.g. DDR5-6000 CL30). Lower CL = faster, but must be weighed against frequency.
The trap: CL is in cycles, not time. Actual latency (ns) = CL / frequency × 2000. DDR5-6000 CL30 ≈ 10 ns; DDR4-3200 CL16 ≈ 10 ns — so equally fast in absolute time despite different CL numbers. Higher frequency often has a higher CL but can still win on bandwidth. For Ryzen, memory timing matters extra (the Infinity Fabric coupling). Other timings (tRCD, tRP, tRAS) exist but CL is mentioned most. Sweet spot 2024: DDR5-6000 CL30 for AM5, DDR5-6400+ for Intel. XMP/EXPO profiles set these timings automatically.