Cache maintenance
The explicit operations firmware has to issue so that the cache and the DMA controller agree on what memory contains.
On a microcontroller without a cache, DMA writes straight to RAM and the CPU reads it from there. The Cortex-M7, which brought a data cache to the microcontroller world in 2014, ended that: the DMA controller bypasses the cache and no hardware keeps the two in step. Before transmitting, the buffer must be cleaned so dirty lines reach RAM. After receiving, it must be invalidated so the CPU stops reading stale copies.
The trap is the 32-byte line size. A buffer that doesn't start and end on a line boundary shares lines with other variables, and invalidating it quietly throws away their fresh writes too. The lazy alternative — have the MPU mark DMA memory non-cacheable — pays in throughput instead of debugging hours, which is often the better trade.