Bus matrix
The crossbar inside a microcontroller that lets the CPU and DMA controllers reach different memories at the same time instead of taking turns on one bus.
A simple bus has one owner at a time: while DMA copies, the CPU waits, which is the classic cycle stealing. A bus matrix, in Arm's terms a multi-layer AHB, gives every master its own path to every slave. The core's instruction bus can fetch from flash while its data bus reads SRAM and two DMA controllers write to peripherals, all in the same clock cycle.
Contention only happens when two masters want the same slave, and then an arbiter decides, usually round-robin. That's why vendors split SRAM into several blocks on separate ports: with the right placement in the linker script, DMA and CPU never fight over the same memory. The block diagram in the reference manual, with all its arrows and crossings, decides whether a real-time requirement can be met — not the clock speed printed on the front page.